Circuit Level Performance of FETS: A Comparative Study of Propagation Delay with Half Adder

نویسندگان

  • Maskura Nafreen
  • Nusrat Ara
  • MD.Imran Hossain
  • Fariha Rahman
چکیده

This paper deals with the propagation delay comparison of half adder with different FETs; such as MOSFET, CNTFET, FINFET. Nanotechnology is the promising field which functions at the molecular level to replace the conventional use of classical CMOS. By simulation, the best part is got that CNTFET shows lesser delay for half adder circuit.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

High-Speed Ternary Half adder based on GNRFET

Superior electronic properties of graphene make it a substitute candidate for beyond-CMOSnanoelectronics in electronic devices such as the field-effect transistors (FETs), tunnel barriers, andquantum dots. The armchair-edge graphene nanoribbons (AGNRs), which have semiconductor behavior,are used to design the digital circuits. This paper presents a new design of ternary half a...

متن کامل

Taguchi Approach and Response Surface Analysis for Design of a High-performance Single-walled Carbon Nanotube Bundle Interconnects in a Full Adder

In this study, it was attempted to design a high-performance single-walled carbon nanotube (SWCNT) bundle interconnects in a full adder. For this purpose, the circuit performance was investigated using simulation in HSPICE software and considering the technology of 32-nm. Next, the effects of geometric parameters including the diameter of a nanotube, distance between nanotubes in a bundle, and ...

متن کامل

Hardware Implementation of "Supplementary Symmetrical Logic Circuit Structure" Concepts

A test chip was fabricated in a standard 1.2-micron CMOS technology using Supplementary Symmetrical Logic Circuit Structure (SUS-LOC) concepts. The test chip demonstrates several ternary logical functions as well as the flexibility of the SUS-LOC structure. Logic functionality and switching performance of the chip were simulated and verified experimentally. Simulated and experimental results ar...

متن کامل

Fast Mux-based Adder with Low Delay and Low PDP

Adders, as one of the major components of digital computing systems, have a strong influence on their performance. There are various types of adders, each of which uses a different algorithm to do addition with a certain delay. In addition to low computational delay, minimizing power consumption is also a main priority in adder circuit design. In this paper, the proposed adder is divided into s...

متن کامل

Power efficient carry propagate adder

Here we describe the design details and performance of proposed Carry Propagate Adder based on GDI technique. GDI technique is power efficient technique for designing digital circuit that consumes less power as compare to most commonly used CMOS technique. GDI also has an advantage of minimum propagation delay, minimum area required and less complexity for designing any digital circuit. We desi...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2017